1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to a method for fabricating reliable interconnect structures in semiconductor integrated circuits.
2. Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include complementary metal oxide semiconductor ("CMOS") devices having diffused source and drain regions that are separated by channel regions, and gates that are located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as CMOS transistors.
Conventionally, a dielectric layer (e.g., silicon dioxide) is deposited over the devices that are formed on a substrate, and via holes are formed through the dielectric layer to the devices below. As is well known in the art, photolithography "patterning" is typically accomplished by depositing a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having via hole patterns, developing the photoresist to form a photoresist via mask, and etching the exposed dielectric layer to form the via holes that lead to a lower level. Once the via holes are formed, a conductive material such as tungsten (W) is used to fill the via holes to define what are known as "tungsten plugs." Once the tungsten plugs are formed, a metallization layer is formed over the dielectric layer and the tungsten plugs. The metallization layer is then patterned using conventional photolithography and plasma etching techniques to define a first level of interconnect metal routing. This process may then be repeated if additional layers of interconnect structures are desired.
To facilitate discussion, FIG. 1 shows a cross-sectional view of a semiconductor substrate 100 having a number of layers fabricated thereon. In this example, the semiconductor substrate 100 has a first dielectric layer 102 deposed over its surface, and a first metallization layer 104 patterned over the first dielectric layer 102. A second dielectric layer 106 is then deposited over the first dielectric layer 102 and the first metallization layer 104. Before a second metallization layer 110 is patterned over the second dielectric layer, via holes are etched and filled with a tungsten material to form tungsten plugs 108. At this point, the second metallization layer 110 is plasma etched to define the desired interconnect lines.
As is well known, conventional plasma etching will cause the semiconductor substrate 100 to be negatively charged, and all metallization features 104/110 and tungsten plugs 108 (i.e., unless they are coupled to the substrate 100) to be positively charged. Once the plasma etching is complete, the substrate 100 is conventionally moved to a basic solution cleaning station where it is submerged in an effort to remove any polymer residues produced during the plasma etching.
Although the basic solution submersing works well in removing the polymer residues, if any one of the tungsten plugs 108 are exposed to the basic solution, the tungsten material will erode away (also known in the art as "corrosion"). As shown in FIG. 1, tungsten plugs 108a are completely covered by the second metallization layer 110, however, a path 120 remains exposing tungsten plug 108b. As mentioned above, because the first metallization layer 104 and the second metallization layer 110 are not coupled to the substrate 100 (i.e., the structure is a floating structure), they will be positively charged and therefore the tungsten plug 108b will erode. If any tungsten plugs 108b erode, the entire IC chip may fail to operate for its intended purpose, thereby driving up fabrication costs.
Because CMOS semiconductor circuits are continuing to decrease in size, and more devices are packed into smaller IC chips, more densely integrated interconnect structures will be required. However, this dense integration has the effect of pushing the limits of conventional photolithography patterning, which necessarily makes photolithography mask misalignments more likely to occur. Of course, when more misalignments occur, more paths 120 will result, thereby increasing the number of exposed tungsten plugs 108b.
In view of the foregoing, there is a need for improved CMOS fabrication techniques that prevent any exposed tungsten plugs from eroding during the basic solvent cleaning operation.